This is a really easy mistake to make if you programmed the register value directly, because the register LSB size is 1 deci-Hertz (i.e. In looking at your configuration, I think the issue is the auxiliary DPLL loop bandwidth. The phase lock threshold value is found int he same drop down as the fill and drain rate. As phase lock is a comparison of the phase relationship between the reference input clock and the feedback clock, if the phase lock threshold (default value of 700 ps) is not configured to account for the input clock noise, then it is easy to see how false unlocks could be declared.
The AD9545 DPLL filters this noise so that the error is not on the feedback clock. Many GPS receivers have up 30 ns of quantization error on their 1 PPS outputs. Sometimes the PLD status blinks on and off due to the noise on the 1 PPS input. When the device is properly configured and in steady state, the phase lock detector will stay solidly high. With respect to the phase lock detector behavior you described. I did not receive a notification for your response. Glad to hear things are starting to work! Sorry, my response is so delayed. If you make all of these changes you should see full phase lock and input/output phase alignment in < 5 minutes. These settings are located in the lock detector settings drop down in the Reference Settings view which is opened by clicking the reference input receiver in the main block diagram.įinally, (this is not your problem because it does not work with phase buildout) for zero-delay operation enable reference sync operation (It can be enabled via the check box in the wizard DPLL drop downs.) I would also recommend increasing the phase/frequency lock fill and drain rates to a value of 200. I'm assuming it is, but figured I would mention it. Make sure the AuxDPLL LD status indicator (on the main block diagram) is green when you are attempting to lock the PLL. I don't see the attached configuration, so this is unconfirmed, but my guess is that your system clock compensation isn't configured quite right. Try the following settings: In this case you will have to perform the "Resolve Error" step for both the Channel 0 and Channel 1.Īs for the lock time. If you need all six 1 Hz outputs, my recommendation would be to synthesize the outputs as: Click this checkbox to have the wizard make the necessary changes to enable tagged feedback operation. Once you make this change to the wizard inputs, a check box labeled "Resolve Error" shoudl appear under the error in the DPLL profile. If you can operate with 1 Hz outputs from just Out0A/Out0B, I would suggest simply setting Out0C = 10MHz. This can be accommodated while still syncing the 1 Hz output with the 1 Hz input by using tagged feedback mode, but of course this requires one of the Channel 0 outputs to be >= 2kHz. The internal zero-delay configuration required a frequency of >= 2 kHz on the feedback TDC. The DPLL/APLL0 for the 1PPS output achieves active ACT in ~1sec, active FLD in ~6min, and active PLD >2hrs.Īll outputs appear stable relative to their references, but not phase aligned.Īttached is my current working configuration using phase buildout settings. The DPLL/APLL1 for the 10MHz output achieves active ACT/FLD/PLD status within a second. I've been able to configure the AD9545 Evaluation board with these sources and generate 1PPS outputs on OUT0A/BC and 10MHz outputs on OUT1A/B using the phase build out configuration in their respective DPLLn Profile 0s. My test set up consist of a Microsemi 8040C Rubidium Clock Synthesizer as the 1PPS and 10MHz GPS reference signals and a 10MHz TXCO 50PPB source for system clock compensation reference. Please let me know what I need to chage in my configuration to make this work and what can I do to speed up 1PPS Frequency and Phase Lock. I've tried mapping the 1PPS reference to either DPLL0 or DPLL1 and neither works. Input or Display lag in Fortnite is really a serious problem which gamers are getting, which can be also easily fixed, if you follow this thread, it is sure you will get your delay issues fix instantly.įor those who has input lags but did not know about Input delay lets understand first what is Input delay in Fortnite.When I attempt to switch DPLL Profile in the Configuration Wizard from "Phase Buildout" to "Int Zero Delay" for the 1PPS I get an error that says "Data Validation Error - criteria does not meet the current configuration". Have you been facing same input delay in Fortnite? Among more than 350 Million players playing Fortnite, ( by Statista) around 10 -20% are facing the input delay lags in the Fortnite, which is not good for the gamers, especially competetive players.Įvery single seconds or say mili seconds are very much crucial for the players, Imagine having a 1v1 with the enemy on competetive match, and got killed by him only because of the input lag you face. How to get less input delay on Fortnite PC?.